Cypress Semiconductor /psoc63 /I2S0 /TX_CTL

Serial data transmission is advanced by 0.5 SCK cycles. This bit is valid only in TX slave mode. When set to ‘1’, the serial data will be transmitted 0.5 SCK cycles earlier than when set to ‘0’.

1. TX_CTL.SCKI_POL=0 and TX_CTL.B_CLOCK_INV=0: Serial data will be transmitted off the SCK falling edge
2. TX_CTL.SCKI_POL=0 and TX_CTL.B_CLOCK_INV=1: Serial data will be transmitted off the SCK rising edge that is 0.5 SCK cycles before the SCK falling edge in 1)
3. TX_CTL.SCKI_POL=1 and TX_CTL.B_CLOCK_INV=0: Serial data will be transmitted off the SCK rising edge
4. TX_CTL.SCKI_POL=1 and TX_CTL.B_CLOCK_INV=1: Serial data will be transmitted off the SCK falling edge that is 0.5 SCK cycles before the SCK rising edge in 3)

(Note that this is only the appearance w.r.t. SCK edge, the actual timing is generated by an internal clock that runs 8x the SCK frequency). The word sync (TX_WS) signal is not affected by this bit setting. Note: When Master mode, must be ‘0’. (Note: This bit is connected to AR38U12.TX_CFG.TX_BCLKINV)

0 (FALLING_EDGE_TX): SDO transmitted at SCK falling edge when TX_CTL.SCKI_POL=0

1 (RISING_EDGE_TX): SDO transmitted at SCK rising edge when TX_CTL.SCKI_POL=0

Specifies number of channels per frame:

Note: only ‘2channels’ is supported during Left Justfied or I2S mode. Hence software must set ‘1’ to this field in the modes. (Note: These bits are connected to AR38U12.TX_CFG.TX_CHSET)

0 (CH_NUM1): 1 channel

1 (CH_NUM2): 2 channels

2 (CH_NUM3): 3 channels

3 (CH_NUM4): 4 channels

4 (CH_NUM5): 5 channels

5 (CH_NUM6): 6 channels

6 (CH_NUM7): 7 channels

7 (CH_NUM8): 8 channels

Set interface in master or slave mode:

(Note: This bit is connected to AR38U12.TX_CFG.TX_MS)

0 (SLAVE): Slave

1 (MASTER): Master

Select I2S, left-justified or TDM:

(Note: These bits are connected to AR38U12.TX_CFG.TX_I2S_MODE)

0 (LEFT_JUSTIFIED): Left Justified

1 (I2S): I2S mode

2 (TDM_A): TDM mode A, the 1st Channel align to WSO Rising Edge

3 (TDM_B): TDM mode B, the 1st Channel align to WSO Rising edge with1 SCK Delay

Set WS pulse width in TDM mode:

(Note: This bit is connected to AR38U12.TX_CFG.TX_WS_PULSE) Note: When not TDM mode, must be ‘1’.

0 (SCK_PERIOD): Pulse width is 1 SCK period

1 (CH_LENGTH): Pulse width is 1 channel length

Set overhead value: ‘0’: Set to ‘0’ ‘1’: Set to ‘1’ (Note: This bit is connected to AR38U12.TX_CFG.TX_OVHDATA)

Set watchdog for ‘tx_ws_in’: ‘0’: Disabled. ‘1’: Enabled.

Channel length in number of bits:

Note:

• When this field is configured to ‘6’ or ‘7’, the length is set to 32-bit (same as ‘5’).
• When TDM mode, must be 32-bit length to this field. (Note: These bits are connected to AR38U12.TX_CFG.TX_CHLEN)

0 (BIT_LEN8): 8-bit

1 (BIT_LEN16): 16-bit

2 (BIT_LEN18): 18-bit

3 (BIT_LEN20): 20-bit

4 (BIT_LEN24): 24-bit

5 (BIT_LEN32): 32-bit

Word length in number of bits:

Note:

• When this field is configured to ‘6’ or ‘7’, the length is set to 32-bit (same as ‘5’).
• Don’t configure this field as beyond Channel length. (Note: These bits are connected to AR38U12.TX_CFG.TX_IWL)

0 (BIT_LEN8): 8-bit

1 (BIT_LEN16): 16-bit

2 (BIT_LEN18): 18-bit

3 (BIT_LEN20): 20-bit

4 (BIT_LEN24): 24-bit

5 (BIT_LEN32): 32-bit

TX master bit clock polarity. When this bit is 1, the outgoing tx_sck signal is inverted after it has been transmitted from the I2S transceiver core. This bit does not affect the internal serial data transmission timing. The word sync (TX_WS) signal is not affected by this bit setting. ‘0’: When transmitter is in master mode, serial data is transmitted from the falling bit clock edge ‘1’: When transmitter is in master mode, serial data is transmitted from the rising bit clock edge

TX slave bit clock polarity. When this bit is 1, the incoming tx_sck signal is inverted before it is received by the I2S transceiver core. This bit does not affect the internal serial data transmission timing. The word sync (TX_WS) signal is not affected by this bit setting. See TX_CTL.B_CLOCK_INV for more details.